{"id":415,"date":"2021-01-30T15:06:06","date_gmt":"2021-01-30T15:06:06","guid":{"rendered":"https:\/\/es-wordpress.fbk.eu\/?p=415"},"modified":"2023-05-09T10:01:35","modified_gmt":"2023-05-09T09:01:35","slug":"verilog2smv","status":"publish","type":"post","link":"https:\/\/es.fbk.eu\/index.php\/tools\/verilog2smv\/","title":{"rendered":"Verilog2SMV"},"content":{"rendered":"\n\n\n[et_pb_section fb_built=&#8221;1&#8243; _builder_version=&#8221;3.22&#8243;][et_pb_row _builder_version=&#8221;3.25&#8243; background_size=&#8221;initial&#8221; background_position=&#8221;top_left&#8221; background_repeat=&#8221;repeat&#8221;][et_pb_column type=&#8221;4_4&#8243; _builder_version=&#8221;3.25&#8243; custom_padding=&#8221;|||&#8221; custom_padding__hover=&#8221;|||&#8221;][et_pb_text _builder_version=&#8221;3.27.4&#8243; background_size=&#8221;initial&#8221; background_position=&#8221;top_left&#8221; background_repeat=&#8221;repeat&#8221;]<!-- divi:paragraph -->\n<p>Verilog2SMV is an open source tool that takes a&nbsp;<a href=\"http:\/\/www.verilog.com\/\">Verilog<\/a>&nbsp;design with simple SystemVerilog assertions and generates a model checking problem at Register Transfer Level in SMV format.<\/p>\n<!-- \/divi:paragraph -->\n\n<!-- divi:paragraph -->\n<p>For further information, please refer to the&nbsp;<a href=\"https:\/\/es.fbk.eu\/tools\/verilog2smv\/\">Verilog2SMV&#8217;s web page<\/a>.<\/p>\n<!-- \/divi:paragraph -->[\/et_pb_text][\/et_pb_column][\/et_pb_row][\/et_pb_section]\n\n\n","protected":false},"excerpt":{"rendered":"","protected":false},"author":1,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_et_pb_use_builder":"on","_et_pb_old_content":"<!-- wp:paragraph -->\n<p>Verilog2SMV is an open source tool that takes a&nbsp;<a href=\"http:\/\/www.verilog.com\/\">Verilog<\/a>&nbsp;design with simple SystemVerilog assertions and generates a model checking problem at Register Transfer Level in SMV format.<\/p>\n<!-- \/wp:paragraph -->\n\n<!-- wp:paragraph -->\n<p>For further information, please refer to the&nbsp;<a href=\"https:\/\/es.fbk.eu\/tools\/verilog2smv\/\">Verilog2SMV's web page<\/a>.<\/p>\n<!-- \/wp:paragraph -->","_et_gb_content_width":"","footnotes":""},"categories":[8],"tags":[],"class_list":["post-415","post","type-post","status-publish","format-standard","hentry","category-tools","et-doesnt-have-format-content","et_post_format-et-post-format-standard"],"_links":{"self":[{"href":"https:\/\/es.fbk.eu\/index.php\/wp-json\/wp\/v2\/posts\/415","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/es.fbk.eu\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/es.fbk.eu\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/es.fbk.eu\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/es.fbk.eu\/index.php\/wp-json\/wp\/v2\/comments?post=415"}],"version-history":[{"count":11,"href":"https:\/\/es.fbk.eu\/index.php\/wp-json\/wp\/v2\/posts\/415\/revisions"}],"predecessor-version":[{"id":9221,"href":"https:\/\/es.fbk.eu\/index.php\/wp-json\/wp\/v2\/posts\/415\/revisions\/9221"}],"wp:attachment":[{"href":"https:\/\/es.fbk.eu\/index.php\/wp-json\/wp\/v2\/media?parent=415"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/es.fbk.eu\/index.php\/wp-json\/wp\/v2\/categories?post=415"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/es.fbk.eu\/index.php\/wp-json\/wp\/v2\/tags?post=415"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}